1. Field of the Invention
The present invention relates generally to testing of electrical circuits and, more particularly, to testing of electrical circuits using scan framing circuits and techniques which allow circuits to be tested in a more efficient manner than achieved using conventional test approaches.
2. Description of Related Art
FIG. 1A illustrates a prior art device 100 having a core 102 with parallel scan paths 104. The core is tested by an external tester inputting stimulus to the scan path inputs, receiving response from the scan paths outputs, and inputting test control to operate the scan paths. This type of testing is well known.
FIG. 1B illustrates a prior art device 106 having a core 108 with parallel scan paths 1110. The stimulus inputs to the scan paths come from a parallel scan distributor (PSC) 112 and the response outputs from the scan paths are input to a parallel scan collector (PSC) 114. The core is tested by an external tester serially inputting stimulus to the PSD via a scan input, serially outputting response from the PSC via a scan output, and inputting test control to operate the PSD, PSC and scan paths. This type of serial to parallel and parallel to serial scan testing was described in U.S. Pat. No. 6,405,335 (Position Independent Testing of Circuits), which is incorporated herein by reference.
FIG. 1C illustrates a prior art device 116 having a core 118 with parallel scan paths 120. The stimulus inputs to the scan paths come from a decompressor (DEC) circuit 122 and the response outputs from the scan paths are input to a compressor (COM) 124, sometimes referred to as a multiple input shift register (MISR) or compactor. The core is tested by an external tester serially inputting compressed stimulus patterns to the DEC via one or more scan inputs, decompressing the stimulus patterns and inputting them to the scan paths, while simultaneously compressing the response outputs from the scan paths in the COM and outputting the compressed response patterns from the COM via one or more scan outputs. The tester inputs control to operate the DEC, COM, and scan paths during test. This type of response compression and stimulus decompression testing is well known as indicated by a paper referenced in the Reference to Related Art section.
FIG. 1D illustrates a prior art device 126 having a core 128 with parallel scan paths 130. The stimulus inputs to the scan paths come from a stimulus pattern generator (GEN) circuit 132 and the response outputs from the scan paths are input to a response pattern compressor (COM) circuit 134. The core is tested by an external tester inputting control to operate the GEN, COM, and scan paths during test. This type of testing is referred to a built in self test (BIST), which is very well known.